1. Field of the Invention
Generally, the present disclosure relates to highly sophisticated integrated circuits including transistor elements having a double gate (FinFET) or triple gate architecture.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for many types of complex circuitry, including field effect transistors, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a planar transistor architecture, on the distance between the source and drain regions, which is also referred to as channel length.
Presently, the vast majority of integrated circuits are based on silicon due to its substantially unlimited availability, the well-understood characteristics of silicon and related materials and processes and the experience gathered during the last 50 years. Therefore, silicon will likely remain the material of choice for future circuit generations designed for mass products. One reason for the dominant importance of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and, thus, allows the performance of subsequent high temperature processes, as are required, for example, for anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, in field effect transistors, silicon dioxide is preferably used as a gate insulation layer that separates the gate electrode, frequently comprised of polysilicon or other metal-containing materials, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has been continuously decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. It turns out that decreasing the channel length for a planar transistor configuration requires an increased capacitive coupling to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a dependence of the threshold voltage on the channel length. Aggressively scaled transistor devices with a relatively low supply voltage and thus reduced threshold voltage may suffer from an exponential increase of the leakage current, while also requiring enhanced capacitive coupling of the gate electrode to the channel region. Thus, the thickness of the silicon dioxide layer has to be correspondingly decreased to provide the required capacitance between the gate and the channel region. The relatively high leakage current caused by direct tunneling of charge carriers through an ultra-thin silicon dioxide gate insulation layer may reach values for an oxide thickness in the range of 1-2 nm that may not be compatible with requirements for performance driven circuits.
In view of further device scaling based on well-established materials, new transistor configurations have been proposed in which a “three-dimensional” architecture may be provided in an attempt to obtain a desired channel width, while at the same time maintaining efficient controllability of the current flow through the channel region. To this end, so-called FinFETs have been proposed in which a thin sliver or fin of silicon may be formed in a thin active layer of a silicon-on-insulator (SOI) substrate, wherein, on both sidewalls, a gate dielectric material and a gate electrode material may be provided, thereby realizing a double gate transistor, the channel region of which may be fully depleted. Typically, in sophisticated applications, the width of the silicon fins is on the order of 10 nm and the height thereof is on the order of 30 nm. In a modified version of the basic double gate transistor architecture, a gate dielectric material and a gate electrode may also be formed on a top surface of the fin, thereby realizing a tri-gate transistor architecture.
Basically, FinFET transistors may provide superior channel controllability since the channel region within the semiconductor fin may be controlled on the basis of at least two, in a double-gate transistor, and three, in a tri-gate transistor, gate portions, wherein, at the same time, the effective channel width may be increased compared to planar transistor configurations so that, for given lateral transistor dimensions, an increased packing density of sophisticated transistors may be provided compared to conventional planar transistor designs. On the other hand, the three-dimensional nature of the semiconductor fin comprising the channel region may result in additional process complexity, for instance for patterning the gate electrode structure, respective spacer elements and the like, wherein, additionally, compatibility with conventional planar transistor architectures may be difficult to be achieved. Moreover, conventional FinFET transistors may suffer from an increased parasitic capacitance and, in particular, a moderately high external resistance, i.e., a resistance for connecting to the drain and source regions, which may mainly be caused by the epitaxially grown additional drain and source material for connecting the individual fin portions at the drain side and the source side of the FinFET transistor on the basis of highly complex epitaxial growth processes.
With reference to FIGS. 1a-1d, the basic configuration of conventional FinFETs and specific characteristics associated with conventional manufacturing techniques will be described in more detail.
FIG. 1a schematically illustrates a perspective view of a semiconductor device 100 that comprises a conventional FinFET transistor 150 on the basis of an SOI substrate. That is, the semiconductor device 100 comprises a substrate 101, such as a silicon substrate, above which is formed a buried insulating layer 102, typically in the form of a silicon dioxide material. Furthermore, a plurality of semiconductor fins 110 are provided and represent the “residues” of a silicon layer (not shown) initially formed on the buried insulating layer 102. The fins 110 comprise a source region 110S and a drain region 110D and a channel region 110C, which is to be considered as the central portion of the fins 110 that connects to the corresponding end portions, i.e., the drain and source regions 110D, 110S. The extension of the channel region 110C along the length direction of the transistor 150, i.e., along the length direction of the fins 110, is determined by a gate electrode structure 120 which comprises an appropriate electrode material 121, such as a polysilicon material and a spacer structure 122 comprised of any appropriate material or material system. It should be appreciated that the gate electrode structure 120 also comprises a gate dielectric material (not shown) that is formed on any surface areas of the channel region 110C that are in contact with the gate electrode structure 120. That is to say, the gate dielectric material (not shown) separates the electrode material 121 from the semiconductor material of the channel region 110C at the sidewalls of the fins 110 and, if a tri-gate transistor is considered, at a top surface of the fins 110. Typical dimensions of the fins 110, for instance for obtaining a fully depleted channel in the channel region 110C, are in the range of 10-12 nm for the fin width, while a height thereof may be selected to be approximately 30 nm.
Typically, the semiconductor device 100 comprising the FinFET 150 is formed by patterning the initially provided silicon layer formed on the buried insulating layer 102, requiring sophisticated lithography and patterning strategies. Prior to or after the patterning of the fins 110, an appropriate well dopant species may be incorporated, wherein, due to the SOI architecture of the transistor 150, any well isolation implantations are not required. Thereafter, the gate electrode structure 120 is formed, for instance by depositing a gate dielectric material and the electrode material 121, possibly including a planarization process due to the pronounced surface topography caused by the plurality of fins 110. During the patterning of the gate electrode structure 120, a complex etch process has to be applied since the patterning process has to stop at two different height levels, i.e., on the top surface of the fins 110 and on the buried insulating layer 102. Similarly, after incorporating appropriate drain and source implantation species for source and drain extension regions, the spacer structure 122 has to be provided on the basis of sophisticated etch techniques, wherein the etch process also has to stop at two different height levels.
As previously discussed, typically, the drain and source resistance may be moderately high for the transistor 150, when the individual semiconductor fins 110 may be connected “externally,” for instance via the contact level of the device 100 that is to be formed in a later manufacturing stage. Consequently, in typical manufacturing strategies, an additional semiconductor material may be grown between the individual semiconductor fins 110 in order to provide a substantially continuous drain and source area (not shown), which may then be contacted by any appropriate contact regime. A corresponding selective epitaxial growth process, however, significantly contributes to the overall process complexity in forming the device 100, wherein, additionally the resulting overall series resistance of the transistor 150, i.e., of the plurality of fins 110, is nevertheless higher than expected so that the overall transistor performance is less pronounced, compared to conventional planar transistors, than expected. Furthermore, significant dopant diffusion into the buried oxide material may occur and may also contribute to inferior drive current capability of the semiconductor fins 110, even if provided with an intermediate epitaxially grown semiconductor material in the drain and source areas.
FIG. 1b schematically illustrates the device 100 wherein the transistor 150 is provided in a “bulk” configuration. That is, the semiconductor fins may be formed in an upper portion of the crystalline substrate material 101, thereby providing an additional silicon volume in the semiconductor fins 110. On the other hand, the electrically “effective” height of the semiconductor fins 110 is adjusted by a dielectric material 102A, for instance in the form of silicon dioxide, which may also electrically isolate the various fins 110. In addition to the dielectric material 102A for defining the electrically effective height of the fins 110 and for laterally isolating the fins, an appropriate isolation structure (not shown) is required for the bulk configuration of the device 100 in FIG. 1b. 
With reference to FIGS. 1c-1d, certain characteristics of the SOI configuration and the bulk configuration, respectively, and any problems associated therewith, will be described in more detail.
FIG. 1c schematically illustrates the semiconductor device 100 according to the SOI configuration, as is also described with reference to FIG. 1a. As discussed above, a resistance, indicated as 105, for connecting to the drain and source regions 110D, 110S is to be reduced by, for instance, epitaxially growing an additional semiconductor material on and between the semiconductor fins 110, followed by an appropriate etch process to remove any excess material so as to provide appropriate conditions for a subsequent silicidation process, however, without significantly contributing to additional parasitic capacitance between the drain and source regions and the gate electrode. The resistance in the semiconductor fins 110 is determined by the width, indicated as 110W, and the height, indicated by 110H, which in turn may be selected so as to obtain a fully depleted transistor behavior. On the other hand, increasing width and/or height may provide a reduced overall resistance of the semiconductor fins 110. Furthermore, overall conductivity of the fins 110 may be affected by a dopant depletion, for instance in drain and source extension regions, i.e., in a region covered by the spacer structure 122, caused by dopant migration into the buried oxide material 102. Moreover, performance of the transistor 150 may be influenced by the parasitic capacitance between the gate electrode and source/drain areas of the fins 110, which could be partially compensated for by selecting shorter and wider fins. Furthermore, as is well known in complex planar transistor architectures, a plurality of performance enhancing mechanisms are implemented, for instance in the form of strain-inducing mechanisms, in order to appropriately modify the charge carrier mobility in the channel region, which directly translates into superior transistor performance. Appropriate strain-inducing mechanisms may be provided in the form of highly stressed dielectric layers formed above the transistors, for instance by providing at least a portion of the interlayer dielectric material of the contact level as a highly stressed material. Any such strain-inducing mechanisms may be less efficient for the configuration as shown in FIG. 1c and thus other appropriate strain-inducing mechanisms may have to be developed. Furthermore, embedded strain-inducing semiconductor materials may generally have a reduced efficiency in SOI configurations, in particular when implemented in the FinFET as shown in FIG. 1c. 
FIG. 1d schematically illustrates the bulk configuration of the device 100, wherein the overall series resistance 105 of the semiconductor fins 110 may be less, compared to the SOI configuration, since, generally, an increased silicon volume may be available in the fins 110 due to the bulk configuration, while, additionally, significant dopant loss into any underlying oxide material is avoided. On the other hand, the resulting parasitic capacitance 104 may be comparable to the SOI configuration, thereby providing, in total, the superior performance of the bulk configuration with respect to the external resistance 105 and the parasitic capacitance 104. Moreover, for vertically isolating the semiconductor fins, a well isolation implantation 106 may be required, which in turn may provide additional potential for appropriately adjusting performance of the device 100 according to a bulk configuration. With respect to strain-inducing mechanisms, any overlying stressed dielectric materials may also be significantly less efficient, comparable to the situation of the SOI configuration described above, while, on the other hand, any embedded strain-inducing semiconductor material may have a somewhat higher efficiency in the bulk configuration, however, with a generally very reduced effect.
Thus, generally, three-dimensional transistor configurations, for instance in the form of SOI and bulk architectures, may provide the potential of increasing transistor performance for given lateral dimensions compared to a planar transistor architecture, wherein, however, additional process complexity may be introduced, for instance, in view of patterning gate electrode structures, providing spacer elements and the like. Furthermore, highly complex epitaxial growth processes may be required to provide appropriate contact resistance in the drain and source areas, which may nevertheless result in a moderately high contact resistance. Additionally, performance enhancing mechanisms, such as stressed dielectric layers, embedded strain-inducing semiconductor materials and the like, may be substantially non-effective, or may have a significantly reduced efficiency compared to planar transistor configurations and may thus require the new development of appropriate mechanisms. Furthermore, conventional FinFET architectures may not be compatible with planar transistor architecture, or may at least require additional process complexity for providing concurrently three-dimensional transistors and planar transistors. For example, for SOI FinFETs, the required height of the semiconductor fins requires the provision of an appropriately thin semiconductor base material which, however, may be inappropriate for forming planar transistors, since a corresponding thickness of approximately 30 nm may not be appropriate for neither fully depleted planar transistors nor for partially depleted SOI transistors. Furthermore, any other passive semiconductor elements may have to be provided in the substrate material. The bulk configuration for forming three-dimensional transistors and planar transistors may require significant process adaptations, for instance with respect to gate patterning processes, spacer etch processes and the like.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.